Advanced Scan Test and Diagnosis Enhances Yield Learning

Manufacturing test and failure analysis remain at the forefront of determining why and how chips fail. Defective chips (i.e., those that fail the production test) offer a goldmine of information. If properly mined, they can provide valuable insight into the defects and failure mechanisms that are limiting yield. The industry standard for testing digital integrated circuits (ICs) after manufacturing is to place them into a piece of automated test equipment (ATE). Various logic test patterns are then run on them to find defects in the circuit. This process is scan test. Most of the test patterns are created by an automated-test-pattern-generation (ATPG) tool. This tool is based on fault models, which are designed to model the various failure behaviors that are found in the ICs when defects are present.